(1) Field of the Invention
The invention relates to an integrated circuit device, and, more particularly, to a differential gain stage capable of low voltage operation.
(2) Description of the Prior Art
Differential gain stages are used in a large variety of electronics circuits. Differential gain stages provide a means of buffering signals and of multiplying voltage and/or current differences between signals. Differential gain stages are one of the key functional features in operational amplifier and/or comparator designs. Differential gain stages typically comprise a pair of transistors. These transistors may be bipolar or MOS.
Referring now to FIG. 1, an example of a prior art differential stage circuit 10 is shown. This differential stage circuit comprises a differential stage 14 and a folded cascode structure 22. The differential stage 14 further comprises a differential pair made up of a first MOS transistor 26 and a second MOS transistor 28, a current source 16 made up of a MOS transistor 24, and a current load 20 made up of a first MOS transistor 30 and a second MOS transistor 32. The folded cascode circuit 22 comprises transistors 34, 36, 38, and 40. In the differential stage 14, a first bias voltage VBP controls the current source transistor 24, and a second bias voltage VBN controls the current load transistors 30 and 32.
During normal operation, the current flowing to the current source transistor 24 is divided between each side of the differential pair 26 and 28 based on the relationship between the first input voltage VI1 and the second input voltage VI2. If VI1 and VI2 are equal, then the current flowing through the current source 24 is divided equally between each side. As a result, the first and second current load transistors 30 and 32 conduct the same amount of current. Because the first and second current load transistors 30 and 32 are biased with the same gate voltage, the voltage outputs VC1 and VC2 of the differential stage 14 are balanced to the same value. The differential stage 14 uses the transconductance of the differential pair transistors 26 and 28 to generate a transfer gain from the input voltage differential to the output voltage differential.
The differential stage 14 relies on an adequate power supply voltage, that is, the voltage difference between VDD and VSS. If the supply voltage drops to a very low level of, for example, about 1 V and, further, if the threshold voltage of the MOS transistors is about 0.65 V, then several problems may occur. First, the current source transistor 24 may come out of saturation mode. As a result, the current flowing through the differential pair 26 and 28 will not be constant over small fluctuations in the power supply voltage. This will cause the differential stage to perform incorrectly unless the voltage bias VBN of the current load transistors 30 and 32 compensates for this problem. Second, the small voltage difference between the power supply and the threshold voltage of the MOS transistors will limit the common mode operating range of the differential pair transistors 26 and 28.
Referring now to FIG. 2, an example of a differential stage 54 used in a common mode regulation circuit 50 is shown. The differential stage 54 again comprises a differential pair 58 and 60, a current source 56, and first and second current loads 62 and 64. The current source 56 is again controlled by a first voltage bias VBP, and the first and second current loads 62 and 64 are controlled by a second current bias VBN. However, in this case, an additional operational amplifier 66 is used to provide a feedback control mechanism between the differential stage outputs VC1 and VC2 and a reference voltage VREF generated by a diode connected transistor 68 conducting a reference current IREF 70. Once again, this application 50 of the differential stage 54 will perform incorrectly at very low voltages if the current source transistor 56 comes out of saturation. Therefore, if the differential pair transistors 58 and 60 do not operate properly due to an inadequate difference between the power supply voltage and the threshold voltage. Reducing the minimum operating voltage of the differential stage is a principal object of the present invention. In addition, the supply voltage to the operational amplifier 66 is also very low. Therefore, this operation amplifier 66 shares the same problems with low supply voltage as the differential stage 54.
Several prior art inventions relate to differential gain stages and amplifiers. U.S. Pat. No. 6,433,638 to Heineke et al teaches a transimpedance amplifier using MESFET devices where a matched pair of source-coupled transistors worse have sources connected to ground to thereby enable low voltage operation. U.S. Pat. No. 6,407,637 to Phanse et al teaches a differential current mirror system with excellent common mode rejection ratio. U.S. Pat. No. 6,538,513 to Godfrey et al teaches an amplifier with common mode output control. U.S. Pat. No. 5,631,606 to Tran et al teaches a differential output CMOS amplifier. In the article, “Low Voltage Analog Circuit Design,” by Rajput et al, in IEEE Circuits and Systems Magazine, Volume 2, Number 1, 1st Quarter 2002, a low voltage analog design technique is shown.